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One of the reasons that the new Celeron performed so poorly, even when overclocked to the same speed, as the Pentium III (i.e. Celeron 850/100 vs Pentium III 850/100) was because the Celeron’s L2 cache featured a 4-way set associative mapping algorithm versus the Pentium III’s 8-way set associative L2 cache. The reason this discrepancy exists is because Intel essentially disables 1/2 of the L2 cache on the Pentium III in order to produce a Celeron (this can be confirmed by noting that the die sizes of the two chips are identical) and by doing that you essentially get half the “associativity”.
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Full View / NID: 4 / Submitted by: TACKtech Team
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Intel to delay new Timna Integrated Processor due to the memory translation hub (MTH) problem. - More 820 problems spreading!
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Full View / NID: 3 / Submitted by: TACKtech Team
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AMD has released the Thunderbird Chips, today.
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Full View / NID: 2 / Submitted by: TACKtech Team
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3dfx has announced that shipping of the Voodoo5 has resumed. The boards should start to reach the gaming public June 9th.
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Full View / NID: 1 / Submitted by: Kevin
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Microsoft program offers ISV partners a boost in the development and certification of Microsoft-based applications.
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Full View / NID: 5638 / Submitted by: The Spirit of Zuron
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